1. Field of the Invention
The present invention relates to an arithmetic unit, and more particularly, it relates to the structure of an arithmetic unit which can functionally execute alternate mark inversion (AMI) coding of an input signal in one machine cycle.
2. Description of the Prior Art
FIG. 1 is a block diagram showing the structure of a conventional basic four-bit arithmetic unit.
Referring to FIG. 1, the conventional arithmetic unit comprises an operation part 100 for performing desired arithmetic operations and a control circuit 10 for designating the type of the arithmetic operation to be performed by the operation part 100.
The control circuit 10 has input terminals 1.sub.S, 2.sub.S, 3.sub.S and 4.sub.S for receiving function selecting signals S.sub.1, S.sub.2, S.sub.3 and S.sub.4 externally supplied for designating the type of arithmetic operation and output terminals H, I and J for respectively outputting control signals T.sub.1, T.sub.2 and C in a prescribed combination in response to the combination of the function selecting signals S.sub.1 to S.sub.4. The control circuit 10 is formed by a PLA (programmable logic array), for example.
In response to the control signals T.sub.1, T.sub.2 and C received from the control circuit 10, the operation part 100 performs the arithmetic operation designated by the function selecting signals S.sub.1 to S.sub.4 on input signals A and B.
The input signal A is formed by four bit signals A.sub.1, A.sub.2, A.sub.3 and A.sub.4 and the input signal B is formed by four bit signals B.sub.1, B.sub.2, B.sub.3 and B.sub.4. The operation part 100 is provided with true and false selecting circuits 21 to 24 each receiving an input signal B.sub.i (i=1 to 4) to output one of B.sub.i, B.sub.i, 1 and 0 in response to the control signals T.sub.1 and T.sub.2 and full adders 31 to 34 each receiving an input signal A.sub.i (i=1 to 4) and output M.sub.i (i=1 to 4) from one of the true and false selecting circuit 21 to 24 and adding up the same to output a sum signal F.sub.i (i=1 to 4) and a carry C.sub.i (i=1 to 4).
The true and false selecting circuit 21 is provided with an input terminal O for receiving the input signal B.sub.1, input terminals P and Q for receiving the control signals T.sub.1 and T.sub.2 respectively and a terminal T for outputting a signal M.sub.1. The full adder 31 is provided with a carry input U for receiving the control signal C from the control circuit 10, input terminals X and Y for receiving the input signals A.sub.1 and M.sub.1 respectively, a terminal V for outputting a sum signal F.sub.1 as the result of addition and a terminal W for outputting a carry C.sub.1.
The true and false selecting circuit 22 is provided with an input terminal O for receiving the input signal B.sub.2, terminals P and Q for receiving the control signals T.sub.1 and T.sub.2 respectively and a terminal R for outputting a signal M.sub.2. The full adder 32 is provided with a terminal U for receiving the carry output from the full adder 31, terminals X and Y for receiving the input signals A.sub.2 and M.sub.2 respectively, a terminal V for outputting a sum signal F.sub.2 as the result of addition and a terminal W for outputting a carry C.sub.2.
The true and false selecting circuit 23 has a terminal O for receiving the input signal B.sub.3, terminals P and Q for receiving the control signals T.sub.1 and T.sub.2 and a terminal R for outputting a signal M.sub.3. The full adder 33 has a terminal X for receiving the input signal A.sub.3, a terminal Y for receiving the signal M.sub.3, a terminal V for outputting a sum signal F.sub.3 as the result of addition, a terminal W for outputting a carry C.sub.3 and a terminal U for receiving the carry C.sub.2 from the full adder 32.
The true and false selecting circuit 24 has a terminal O for receiving the input signal B.sub.4, terminals P and Q for receiving the control signals T.sub.1 and T.sub.2 respectively and a terminal R for outputting a signal M.sub.4. The full adder 34 has a terminal U for receiving the carry C.sub.3 from the full adder 33, a terminal X for receiving the input signal A.sub.4, a terminal Y for receiving the signal M.sub.4, a terminal V for outputting a sum signal F.sub.4 as the result of addition and a terminal W for outputting a carry C.sub.4.
The aforementioned structure is adapted to output A+M+C through combination of the control signals T.sub.1, T.sub.2 and C.
FIG. 2 is a logic diagram showing specific structure of each true and false selecting circuit as shown in FIG. 1. Referring to FIG. 2, the true and false selecting circuit is provided with an AND gate 41 for receiving an input signal B.sub.i and the control signal T.sub.2, an inverter 40 for inverting the input signal B.sub.i and outputting the same, an AND gate 42 for receiving output B.sub.i from the inverter 40 and the control signal T.sub.1 and an OR gate 43 for receiving the outputs from the AND gates 41 and 42 to output a signal M.sub.i.
In the aforementioned structure, one of B.sub.i, B.sub.i, 1 and 0 is selectively outputted as the signal M.sub.i in accordance with the control signals T.sub.1 and T.sub.2, in the following manner:
(1) When T.sub.1 ="0" and T.sub.2 ="0":
Both of the AND gates 41 and 42 are disabled to output "0". Thus,
M.sub.i ="0" PA1 M.sub.i =B.sub.i PA1 M.sub.i =B.sub.i, i.e., complement on B.sub.i is transferred. PA1 M.sub.i ="1" PA1 (1) If A&lt;B, then output 1; PA1 (2) If -A.ltoreq..vertline.B.vertline..ltoreq.A, then output 0; and PA1 (3) If B&lt;-A, then output -1.
(2) When T.sub.1 ="0" and T.sub.2 ="1":
The AND gate 41 is enabled and the AND gate 42 is disabled. Thus, the AND gate 42 outputs B.sub.i and the AND gate 41 outputs "0", and hence:
(3) When T.sub.1 ="1" and T.sub.2 ="0":
The AND gate 41 is disabled and the AND gate 42 is enabled. Thus, the AND gate 41 outputs "0" and the AND gate 41 outputs B.sub.i, and hence,
(4) When T.sub.1 ="1" and T.sub.2 ="1":
Both of the AND gates 41 and 42 are enabled. Since either B.sub.i or B.sub.i is "1", one input of the OR gate 43 is "1" and hence:
Thus, the true and false selecting circuit outputs one of B.sub.i, B.sub.i, 1 and 0 as the signal M.sub.i by combination of the control signals T.sub.1 and T.sub.2.
Since the four full adders 31 to 34 form a four-bit adder, four-bit output F=(F.sub.1, F.sub.2, F.sub.3, F.sub.4) from the full adder 31 to 34 is: EQU F=A+M+C
The values of M and C are decided through combination of the function selecting signals S.sub.1 to S.sub.4, whereby the arithmetic unit can perform arithmetic operation designated by the function selecting signals S.sub.1 to S.sub.4 with respect to the input signals A and B to output the same.
Relation between the control signals T.sub.1, T.sub.2 and C and the output F is as shown in Table 1, whereby eight types or arithmetic operation can be performed.
TABLE 1 ______________________________________ T.sub.1 T.sub.2 C M.sub.i Operation Output Function ______________________________________ 0 0 0 0 F = A transfer A 0 0 1 0 F = A + 1 increment A 0 1 0 B F = A + B add B to A 0 1 1 B F = A + B + 1 add B to A + 1 1 0 0 .sup.--B F = A + .sup.--B add one's complement on B to A 1 0 1 .sup.--B F = A + .sup.--B + 1 add two's complement on B to A 1 1 0 1 F = A - 1 decrement A 1 1 1 1 F = A transfer A ______________________________________ *i = 1, 2, 3, 4
Consider that the input signal A is a threshold value (input signal A is assumed to be positive), which is compared with the input signal B to perform three-level decision as follows:
In fact, this three-level decision corresponds to AMI (alternate mark inversion) coding usually employed in the field of wired digital transmission.
Such AMI coding is performed in a line terminals such as a short-haul modem in a baseband transmission system. Such a line terminals is employed for relatively local connection of a computer and a terminal or extension of an external dedicated line. This line terminals is further adapted to transfer digital data from a subscriber to a nearby station in order to connect the subscriber's terminal to a digital data network.
FIGS. 3(a) and 3(b) are diagrams for illustrating AMI coding. FIG. 3(a) shows exemplary behavior of the input signal B with respect to the input signal A (threshold value), and FIG. 3(b) shows relation between the value of the input signal B and those of threshold values A and -A.
As shown in FIG. 3(a), the input signal B is sampled at predetermined time interval to compare the sampled value B with the threshold values A and -A. In response to relation between the sampled value B and the threshold values A and -A, one of the values 1, 0 and -1 is outputted as shown in the above expression (1), (2) or (3). The input signal B is thus AMI coded.
The arithmetic unit as shown in FIG. 1 has no function for three-level decision although the same can perform arithmetic operation, as obvious from the above description. Thus, the conventional arithmetic unit cannot perform AMI coding of the input signal B. Therefore, a register or the like is generally prepared in addition to the conventional arithmetic unit to perform AMI coding through software technique such as microprogram control.
FIG. 4 shows the algorithm for performing AMI coding in a software manner.
In this algorithm, AMI coding of an input signal B is performed through prescribed storage regions D and E of a register or a storage unit such as a memory. Referring to FIG. 4, description is now made on the AMI coding performed in a software manner.
First, a determination is made as to whether the input signal B is positive or negative (step 1). When B.gtoreq.0, "1" is stored in the storage region D (step 2). Then difference A-B between the threshold value A and the input signal B is stored in the storage region E. If the input signal B is negative (B&lt;0), -1 is stored in the storage region D (step 4). Then, the sum A+B of the threshold value A and the input signal B is stored in the storage region E.
Thereafter a determination is made as to whether the value stored in the storage region E (i.e., A-B, if B.gtoreq.0; A+B, if B&lt;0) is positive or negative (step 6). When the value stored in the storage region E is equal to or larger than zero, i.e., when E.gtoreq.0, "0" is stored in the storage region D (step 7). Then the value stored in the storage region D is outputted. If E&lt;0 at the step 6, the current value stored in the storage region D is outputted.
In this algorithm, the value of the input signal B is compared with that of the input signal A being a threshold value after a determination is made as to whether the input signal B is positive or negative, to output AMI code. However, this algorithm includes two condition judgements as well as substitution and arithmetic operation, whereby at least several machine cycles are required for executing AMI coding.
Thus, the conventional arithmetic unit has no function for AMI coding of an input signal, and hence the input signal has been generally AMI coded in a software manner. Thus, several machine cycles have been required for executing AMI coding of the input signal, leading to increase in time.
The structure of the operation part of the aforementioned arithmetic unit and the design logic of a general arithmetic unit are described in "Digital Logic and Computer Design" by M. MORRIS MANO, Chapter 2, Sections 2.4 to 2.6, 1979, published by Prentice-Hall and translated into Japanese and published by Kyoritsu Shuppan.
Related art of the present invention is described in "Arithmetic and Logic Operation Unit", U.S. patent application Ser. No. 021,666 corresponding to Japanese Patent Application No. 31121/1986 filed in the name of the inventor and assigned to the assignee of this case. This related art is different in idea of the algorithm for AMI coding from the present invention, and is complicated in circuit structure.